The present invention relates to a technique regarding image processors for recording image data acquired by solid-state imaging devices on media.
In recent years, with increase in the number of pixels processed by imaging devices, it has become more and more necessary for devices such as digital still cameras and camera-equipped cellular phones to process images with a large number of pixels at higher speed. In addition, demand for continuous shooting function similar to that of silver salt cameras has been growing. To increase the number of pictures that can be continuously shot and to process these pictures at high speed, a memory region needs a large capacity in proportion to the number of pictures to be continuously shot.
FIG. 6 is an example of configuration of a known image processor. The image processor obtains JPEG-compressed image data from an output signal from a CCD solid-state imaging device 202 that produces a progressive output, and records the obtained data on a medium 213. The solid-state imaging device 202 is driven by a transfer pulse signal output from a timing generator 201 and outputs a pixel potential signal according to a pixel charge of a captured image. The pixel potential signal output from the solid-state imaging device 202 is subjected to noise reduction by a correlated dual sampling circuit 203, quantized by an A/D converter 204, and then supplied, as image data, to a writing controller 206 in a memory controller 205.
As shown in FIG. 7A, the writing controller 206 writes the image data in a memory 208 in order from a write start address. As in the pixel arrangement of the solid-state imaging device 202, when writing of the image data for one horizontal line is completed, the position of writing vertically shifts to a next line and then horizontally returns to the original position on the next line so that writing for the next horizontal line is performed. Then, such writing operation continues until a screenful of image data is completely written in the memory 208.
When a screenful of image data is completely written in the memory 208, a reading controller 207 in the memory controller 205 reads the image data by Y/C processing blocks, as shown in FIG. 7B. The image data that has been read out by blocks is supplied to a Y/C processing section 209. The Y/C processing section 209 generates luminance signals Y and color-difference signals Cr•Cb from the image data by blocks, and these signals are sent to a JPEG processing section 210. When the luminance signals and the color-difference signals by JPEG processing blocks are accumulated in the JPEG processing section 210, JPEG-compression coding starts and coded data is output. The output coded data is written in the memory 208 by the writing controller 206.
When a screenful of coded data, i.e., JPEG-compressed image data, is written in the memory 208, the JPEG-compressed image data read out from the memory 208 is recoded on a recording medium 213 via a CPU bus in accordance with an instruction given by a CPU 212.
FIG. 8 shows another example of configuration of the known image processor (see Japanese Unexamined Patent Publication No. 2001-285776). In FIG. 8, improvements are made to the configuration shown in FIG. 6 so that high-speed processing is implemented and an image with a large number of pixels is coded in a small memory region. Specifically, a memory controller 205A includes a drive stop controller 214. The drive stop controller 214 stops a transfer pulse from the timing generator 201 to the solid-state imaging device 202 and controls stopping/driving of both the Y/C processing section 209 and the JPEG processing unit 210, in accordance with the positional relationship between a writing address at which pixel data is written in the memory 208 and a data-block reading address. This allows writing for the next screen to start before coding for the current screen is completed in continuous shooting. Accordingly, image coding is performed at higher speed than in conventional processing. If at least two line areas each including a minimum unit block for JPEG processing, i.e., M×2 lines, are provided as shown in FIGS. 9A and 9B, JPEG processing for one screen is implemented. Therefore, a screenful of image data does not need to be completely stored in the memory 208 to generate a screenful of coded data, thus reducing the memory capacity.